{"slug":"matlab-matlab-dsphdl-ddc-design","source_name":"matlab/matlab-dsphdl-ddc-design","name":"Matlab/Matlab Dsphdl Ddc Design","description":"Use when designing a Digital Down Converter (DDC) using dsphdl System objects. Triggers on requests involving DDC design, frequency down-conversion for FPGA/ASIC, NCO + mixer + decimation filter chains, fractional/non-integer sample rate conversion, or HDL-optimized receiver front-end signal processing.","version":1,"lift":{"pass_rate_delta_pts":36.36,"pass_rate_pct":81.8,"total_cases":22,"passed_cases":18,"tokens_delta_pct":167.1,"turns_delta_pct":0,"verdict":"mixed","benchmark_model":"gemini-3.6-flash","grading_method":"judged","completed_at":"2026-08-16T18:05:43.925692+00:00"},"skill_score":null,"benchmark_models":[{"model":"gemini-3.6-flash","headline":true,"delta_pts":36.36,"with_pass_pct":81.8,"without_pass_pct":45.5,"tokens_delta_pct":167.1,"turns_delta_pct":0,"total_cases":22,"cases_aggregated":22,"verdict":"mixed","never_hurt":false,"completed_at":"2026-08-16T18:05:43.925692+00:00","run_id":"4b917071-cb98-40f8-b2bf-ea2ff9e23ff7","version_number":1,"is_latest_version":true,"gate":null}],"trust":{"skill_safety":"passed","safety_status":"clean","intent_verdict":"safe","content_status":"clean","indexable":true},"license":"https://www.mathworks.com/content/dam/mathworks/license/pmrl/license.md","install_count":0,"manifest_hash":"e7a6440de76f2458a73594571706bda1cee762c71c916eae89e1074023ac143c","raw_url":"https://app.decimal.ai/s/matlab-matlab-dsphdl-ddc-design/SKILL.md","scorecard_url":"https://app.decimal.ai/skills/matlab-matlab-dsphdl-ddc-design"}