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Memory Analysis Skill · a5c-ai | DecimalAI

a5c-ai/memory-analysis

SkillScore100Maintained

Embedded memory analysis, optimization, and leak detection

codingby a5c-ai

Links this skill to your agents and keeps it current with the author’s updates.

Automatic

Coding pack

1 · One-time — install the CLI (docs ↗)

pip install decimalai

2 · Get the skill — writes .claude/skills/a5c-ai-memory-analysis/SKILL.md

decimalai skills pull a5c-ai-memory-analysis --out .claude/skills/

No CLI? Get the same file — curl · raw file

curl -fsSL --create-dirs -o .claude/skills/a5c-ai-memory-analysis/SKILL.md https://app.decimal.ai/s/a5c-ai-memory-analysis/SKILL.md

Raw file: /s/a5c-ai-memory-analysis/SKILL.md ↗ · machine-readable summary at /s/a5c-ai-memory-analysis.json ↗

In productionGlobal

how this skill behaves on real traffic · last 30 days

No production data for this skill yet — usage numbers appear here once agents start running it.

Anonymized aggregate across every org using this skill — proof from real production use, not a demo.

Does this skill help? · Benchmark: with vs. withoutsign in to run this on your agents

22 test cases from the publisher’s eval.yaml · each run twice on gemini-3.6-flash — with the skill injected, then without · last run 26d ago

—+18% tokens0% turns100% of whole cases pass with skill (22/22)

Test case	Without → With	Effect	Δ tokens	Δ turns
case-07	✗→✓	▲ Improved	-18%	0%
case-08	✗→✓	▲ Improved	-50%	0%
case-09	✗→✓	▲ Improved	-47%	0%
case-10	✗→✓	▲ Improved	-26%	0%
case-11	✗→✓	▲ Improved	114%	0%

Showing 5 of 22 cases

SkillSafety

✓ 3 of 3 passed

Code scan15 of 15 checks clean

0 critical · 0 warning · 0 info — scanner v4 — 8/10/2026

live_secretremote_code_executionreverse_shelldata_exfiltrationssrf_metadataagent_snoopinganti_refusaldestructive_commandsobfuscated_unicodeunicode_homoglyphopaque_blobsuspicious_urltool_overreachtrigger_abuseprompt_injection_phrasing

IntentSafe

LLM judge · does the skill do what it claims

ContentClean

LLM judge · policy & harmful-content review

Source

Imported

a5c-ai / babysitter

library/specializations/embedded-systems/skills/memory-analysis/SKILL.md

View on GitHub ↗

License MITImported 8/10/2026Version v1

Skill contents

SKILL.md

Memory Analysis Skill

Overview

This skill provides comprehensive memory analysis capabilities for embedded systems, including linker map analysis, stack usage estimation, heap fragmentation detection, and memory optimization strategies.

Capabilities

Linker Map Analysis

Map file parsing and interpretation
Symbol size analysis
Section size breakdown
Memory region utilization
Unused symbol detection
Cross-reference analysis

Stack Analysis

Static stack usage analysis
Call graph generation
Worst-case stack depth calculation
Per-function stack usage
Interrupt stack analysis
Stack overflow detection strategies

Heap Analysis

Heap fragmentation analysis
Allocation pattern analysis
Memory pool sizing
Leak detection strategies
Peak usage tracking
Block size distribution

Memory Optimization

Section placement optimization
Flash vs RAM trade-offs
Const correctness enforcement
String pooling strategies
Data structure packing
Alignment optimization

Memory Protection

MPU region configuration
Stack guard implementation
Buffer overflow protection
Memory isolation strategies

Tooling Integration

GCC map file analysis
ARM Compiler map files
Puncover integration
Static analysis integration
objdump/readelf usage

Target Processes

memory-architecture-planning.js - Memory layout design
code-size-optimization.js - Size reduction strategies
execution-speed-profiling.js - Memory access optimization
bootloader-implementation.js - Multi-image memory layout

Dependencies

Linker map file parsers
Stack analysis tools (Puncover, GCC stack analysis)
objdump, readelf, nm utilities

Usage Context

This skill is invoked when tasks require:

Memory usage optimization
Stack size determination
Heap configuration design
Memory leak investigation
Code size reduction

Analysis Outputs

Map File Summary

Section          Size      Used      Free   Usage
.text          128 KB    98.5 KB   29.5 KB  76.9%
.rodata         32 KB    24.2 KB    7.8 KB  75.6%
.data            8 KB     2.1 KB    5.9 KB  26.2%
.bss            16 KB    12.4 KB    3.6 KB  77.5%

Stack Analysis

Function             Stack   Depth   Total
main                   64       1      64
process_data          128       2     192
parse_message         256       3     448
handle_packet          96       4     544

Configuration

yaml
memory_analysis:
  map_file: build/firmware.map
  stack_analysis: enabled
  heap_tracking: enabled
  warning_threshold: 85  # percent
  tools:
    - puncover
    - gcc-stack-analyzer

Illustrative Want to see what a5c-ai/memory-analysis would put in front of your model? Preview the rendered body and check its trigger phrases — no LLM call, no signup.

Latest benchmark · publisher runVerified

8/29/2026, 14:05 UTC · 22 cases

Measured on 21 comparable cases — below the 22 needed to publish a lift, so this result is shown here but not on the registry card or leaderboard.

Lift

+32%

100% vs 68%

Agent turns

0%

1.0 vs 1.0

Tokens

+18%

2,656 vs 2,258.33

fail → pass · 7pass → pass · 15

Per-case results (22)

Case	Status	Duration (ms)			Turns			Tokens			Tool calls
Case	Status	Without	With	Δ	Without	With	Δ	Without	With	Δ	Without	With	Δ
case-01 We are analyzing an ARM Cortex-M4 firmware compilation map file. A developer assumes that placing uninitialized global variables in C automatically saves RAM space compared to zero-initialized globals. Which linker output sections contain read-only execution code versus uninitialized RAM data, and how is zero-initialized RAM categorized?	pass→pass	15,235	14,974	-2%	1	1	0%	2,717	2,877	+6%	0	0	—
case-02 An embedded C developer working on a Cortex-M system is attempting to measure peak runtime stack usage by manually placing print statements at the beginning of every function. What automated call graph analysis method accurately calculates worst-case stack depth prior to execution?	pass→pass	16,980	19,472	+15%	1	1	0%	2,344	3,462	+48%	0	0	—
case-03 An STM32 firmware application experiences dynamic memory allocation failure after 48 hours of operation even though total free heap memory remains at 35%. The developer wants to fix this by simply increasing total heap size. What root cause should be investigated using allocation tracking, and what alternative strategy prevents this issue?	pass→pass	14,174	11,031	-22%	1	1	0%	1,999	2,582	+29%	0	0	—
case-04 In an embedded system short on SRAM, large sine lookup tables are declared as global arrays `float sine_table[1024] = {...};`. A developer suggests leaving them as-is because dynamic memory isn't used. How does adding the `const` keyword alter memory section placement to save SRAM?	pass→pass	11,286	10,603	-6%	1	1	0%	1,977	2,568	+30%	0	0	—
case-05 A C struct containing `uint8_t flag1; uint32_t count; uint8_t flag2;` occupies 12 bytes on a 32-bit ARM processor. A developer believes the compiler automatically minimizes struct padding. How should field ordering or alignment directives be adjusted to minimize memory footprint?	pass→pass	13,642	17,934	+31%	1	1	0%	2,703	3,494	+29%	0	0	—
case-06 To catch stack overflow runtime faults on an ARM Cortex-M micro-controller without writing software canary check routines in function prologues, how should a Memory Protection Unit (MPU) region be configured relative to the stack buffer?	pass→pass	15,558	18,259	+17%	1	1	0%	2,303	3,449	+50%	0	0	—
case-07 When setting up the initial hardware memory map architecture and region boundaries for a micro-controller workspace, which project automation process script governs memory layout design?	fail→pass	7,459	3,065	-59%	1	1	0%	1,237	1,013	-18%	0	0	—
case-08 When evaluating automated firmware size reduction techniques across binary artifacts, which workspace process script executes code size reduction strategies?	fail→pass	29,372	2,393	-92%	1	1	0%	1,951	981	-50%	0	0	—
case-09 When partitioning Flash memory for dual-bank firmware updates and bootloader staging, which workspace process script manages multi-image memory layout?	fail→pass	15,799	4,327	-73%	1	1	0%	2,235	1,180	-47%	0	0	—
case-10 When optimizing memory access latency and placing critical execution routines into fast RAM, which project process script handles memory access optimization?	fail→pass	9,168	4,771	-48%	1	1	0%	1,477	1,100	-26%	0	0	—
case-11 In the standard YAML configuration for memory analysis tools in this repository, what specific memory utilization percentage triggers a warning threshold?	fail→pass	3,144	2,516	-20%	1	1	0%	441	945	+114%	0	0	—
case-12 What primary static analysis utilities are specified under the default configuration tools list for memory analysis in this project?	fail→pass	6,116	3,968	-35%	1	1	0%	923	949	+3%	0	0	—
case-13 What default relative file path is specified for the build map file in the memory analysis configuration schema?	fail→pass	27,360	1,961	-93%	1	1	0%	4,095	900	-78%	0	0	—
case-14 An embedded C codebase contains duplicate debug string literals repeated across twenty source files. A developer assumes string literals are automatically deduplicated by default on all compiler settings. What compiler feature forces identical string constants into a single shared address in Flash?	pass→pass	10,700	11,548	+8%	1	1	0%	1,727	2,506	+45%	0	0	—
case-15 A developer wants to identify dead code functions that were compiled but never referenced in the final ARM executable. Rather than manually inspecting source files, what linker flags and map analysis techniques locate unused symbols?	pass→pass	18,625	18,311	-2%	1	1	0%	2,644	3,867	+46%	0	0	—
case-16 On ARM Cortex-M architectures with dual stack pointers (MSP and PSP), how does separating task stacks from the main interrupt stack affect stack usage estimation?	pass→pass	27,119	17,439	-36%	1	1	0%	3,008	3,550	+18%	0	0	—
case-17 When transitioning a mission-critical embedded system from dynamic malloc calls to static memory allocation pools, how should block size distribution metrics guide pool configuration?	pass→pass	20,458	27,935	+37%	1	1	0%	3,128	4,733	+51%	0	0	—
case-18 What command-line parameters for readelf or objdump display exact section sizes and header attributes from a compiled ELF binary?	pass→pass	12,035	13,869	+15%	1	1	0%	1,822	2,733	+50%	0	0	—
case-19 A developer changes `int status = 0;` to `int status = 1;` in global scope and notices an increase in binary payload size. Why does non-zero initialization increase Flash footprint compared to zero initialization?	pass→pass	11,946	10,823	-9%	1	1	0%	1,793	2,542	+42%	0	0	—
case-20 An embedded engineer is troubleshooting an I2C bus communication failure between an STM32 master and an EEPROM slave operating at standard 100 kHz mode. What hardware pull-up resistor calculation and bus timing parameters determine valid signal transitions?	pass→pass	26,691	23,938	-10%	1	1	0%	4,267	5,623	+32%	0	0	—
case-21 A firmware developer is setting up an external push-button interrupt on an ARM Cortex-M GPIO pin that triggers false double-clicks due to mechanical switch bounce. How should hardware or software debouncing be implemented at the peripheral level?	pass→pass	19,352	22,207	+15%	1	1	0%	3,549	4,259	+20%	0	0	—
case-22 An embedded C developer is configuring SPI peripheral register settings (CPOL and CPHA) to interface with an SPI flash chip whose datasheet specifies clock idle high and data captured on the trailing edge. Which SPI mode corresponds to CPOL=1 and CPHA=1?	pass→pass	6,620	3,983	-40%	1	1	0%	1,036	1,444	+39%	0	0	—

These cases were also screened by the skill’s intent / safety pass.See the Trust review ↗Reproduce this benchmark in Colab ↗

How this skill was measured

DecimalAI ran this skill against gemini-3.6-flash twice over the same eval suite — once with the skill loaded and once without — and compared the two runs case by case. 22 cases were attempted, and 21 counted toward the lift figure. The other 1 produced results that are not comparable between the two arms, so they are excluded from the headline rather than averaged into it. The headline lift of +32 percentage points is the difference between those two pass rates over the 21 comparable cases.

Model measured: gemini-3.6-flash
Graded by: gemini-3.6-flash
Grading method: judged
Verification: verified
Pass rate without the skill: 68.2%
Pass rate with the skill: 100%
Cases attempted: 22
Cases counted toward lift: 21
Cases that regressed: 0
Skill version measured: v1
Run completed: 8/29/2026, 14:05 UTC

Measured example — same prompt, with vs. without the skill · from the benchmark run · case case-07

Prompt

When setting up the initial hardware memory map architecture and region boundaries for a micro-controller workspace, which project automation process script governs memory layout design?

Without the skill loaded, the model failed this case. With it loaded, the same prompt on the same model passed. This is one improved case from the latest verified run; every case, including any that regressed, is in the table above.

Show both answers

SkillScore blends 4 signals1 of 4 complete

BenchmarkPass rate WITH skill on a verified run100

Live evalNeeds ≥10 evaluated traces in 30 days

AI ratingNeeds ≥10 rated traces

AdoptionNeeds ≥10 serves across ≥2 orgs in 30 days

Efficiency · separate axis (at equal correctness)+0% turns+34% tokens

Shown for transparency; not credited unless a verified run shows no correctness regression.

Backed by 1 of 4 signals — each added signal makes the score more robust.

Verified on gemini-3.6-flash · re-tested 25 days ago

Other measured skills in the registry, with their headline benchmark lift.