▸case-01 We are developing a lightweight JIT compiler pipeline for our custom runtime environment and need to establish a register allocation architecture. Please evaluate our execution model and output a JSON configuration object detailing the chosen allocation algorithm, the spill strategy, the relevant register classes, and any generated source files. | fail→pass | 14,658 | 9,817 | -33% | 1 | 1 | 0% | 2,847 | 2,018 | -29% | 0 | 0 | — |
▸case-02 I'm building an ahead-of-time code generation backend for an LLVM IR pass where compile time is less critical than runtime execution speed. Provide a complete register allocation plan formatted as a JSON object containing the algorithm string, spill strategy details, register classes list, and the resulting generated files. | fail→pass | 28,633 | 7,234 | -75% | 1 | 1 | 0% | 6,460 | 1,709 | -74% | 0 | 0 | — |
▸case-03 Our team is updating the native code emitter inside our bytecode VM implementation to handle high register pressure loops with caller/callee save constraints. Please generate a register allocation setup report in JSON format with fields for the selected allocation algorithm, spill strategy, register classes, and generated file artifacts. | fail→pass | 18,263 | 4,906 | -73% | 1 | 1 | 0% | 4,006 | 1,398 | -65% | 0 | 0 | — |
▸case-04 We are building a WebAssembly JIT engine where compilation delay directly impacts user-perceived page load latency. We want optimal runtime performance, so we are considering spending extra compilation time on Chaitin-Briggs graph coloring. Output a JSON configuration object with 'algorithm', 'spillStrategy', 'registerClasses', and 'generatedFiles'. | fail→pass | 8,292 | 9,977 | +20% | 1 | 1 | 0% | 1,734 | 2,250 | +30% | 0 | 0 | — |
▸case-05 Our CI/CD build matrix compiles C++ binaries statically using an LLVM backend. Developers want faster build times, so someone suggested using linear scan allocation in release compiler binaries. Produce a JSON configuration object with 'algorithm', 'spillStrategy', 'registerClasses', and 'generatedFiles'. | fail→fail | 5,884 | 5,328 | -9% | 1 | 1 | 0% | 1,181 | 1,420 | +20% | 0 | 0 | — |
▸case-06 When setting up a graph-coloring register allocator pipeline for an x86-64 backend, a developer suggests running move instruction coalescing prior to computing virtual register live ranges to save analysis time. How should the pipeline ordering be structured between live range computation and allocation? | pass→pass | 17,853 | 20,062 | +12% | 1 | 1 | 0% | 2,966 | 3,936 | +33% | 0 | 0 | — |
▸case-07 In an AOT register allocator, virtual register V1 is accessed 5 times inside a loop nested 3 levels deep, while virtual register V2 is accessed 10 times in straight-line code outside loops. A developer proposes spilling V1 because its static instruction access count is lower than V2. Which variable should be prioritized for spilling? | pass→pass | 9,322 | 7,300 | -22% | 1 | 1 | 0% | 1,631 | 1,735 | +6% | 0 | 0 | — |
▸case-08 During graph-coloring register allocation, an optimization pass attempts aggressive register coalescing on virtual registers linked by move instructions. What is the explicit code quality benefit achieved by this coalescing pass? | pass→pass | 7,482 | 7,004 | -6% | 1 | 1 | 0% | 1,239 | 1,420 | +15% | 0 | 0 | — |
▸case-09 A virtual register in an x86-64 function has a live range spanning the entire function body, but it is only actively read in two small, distant basic blocks separated by heavy computations. Spilling it globally incurs store and load overhead across blocks where it is unread. What register allocation technique minimizes spill overhead by dividing long live ranges? | pass→pass | 10,355 | 13,121 | +27% | 1 | 1 | 0% | 1,800 | 2,708 | +50% | 0 | 0 | — |
▸case-10 In a x86-64 System V ABI implementation with caller-saved (%rax, %rcx, %rdx) and callee-saved (%rbx, %r12, %r13) registers, how should a register allocator assign physical registers for virtual registers that remain live across subroutine call instructions? | pass→pass | 15,433 | 17,920 | +16% | 1 | 1 | 0% | 2,833 | 3,660 | +29% | 0 | 0 | — |
▸case-11 In an Interference Graph for an x86-64 function, fixed architecture registers like %rax (used for return values) are added as pre-colored nodes. During the graph simplification phase, can the allocator change the assigned color of a pre-colored node or spill it? | pass→pass | 12,208 | 11,864 | -3% | 1 | 1 | 0% | 2,020 | 2,612 | +29% | 0 | 0 | — |
▸case-12 When designing a register pressure analysis pass for an IR basic block before instruction scheduling, how should the pass calculate the peak register pressure? | pass→pass | 18,767 | 18,563 | -1% | 1 | 1 | 0% | 3,423 | 3,240 | -5% | 0 | 0 | — |
▸case-13 When a register allocator decides to spill a virtual register V to stack frame memory in an x86-64 function, at what precise locations in the instruction stream must spill load instructions be inserted? | pass→pass | 18,857 | 23,747 | +26% | 1 | 1 | 0% | 3,052 | 3,920 | +28% | 0 | 0 | — |
▸case-14 We are designing a bytecode VM native emitter that utilizes a second-chance binpacking register allocator. Provide a complete JSON configuration object containing 'algorithm', 'spillStrategy', 'registerClasses', and 'generatedFiles'. | fail→pass | 17,555 | 4,427 | -75% | 1 | 1 | 0% | 3,644 | 1,272 | -65% | 0 | 0 | — |
▸case-15 A virtual register V is assigned to a caller-saved physical register in an ARM64 function. If V must survive across a function call instruction (`BL`), what spill code must be emitted around that call site? | pass→pass | 11,612 | 12,283 | +6% | 1 | 1 | 0% | 2,065 | 2,710 | +31% | 0 | 0 | — |
▸case-16 When constructing an undirected interference graph for Chaitin-Briggs graph coloring, under what exact condition is an edge added between virtual register node A and virtual register node B? | pass→pass | 11,172 | 11,811 | +6% | 1 | 1 | 0% | 1,890 | 2,481 | +31% | 0 | 0 | — |
▸case-17 Our game engine script compiler generates ARM64 machine code dynamically at 60 FPS. We need a register allocation strategy that minimizes compilation delay during gameplay. Generate a JSON configuration object with keys 'algorithm', 'spillStrategy', 'registerClasses', and 'generatedFiles'. | pass→pass | 14,027 | 4,181 | -70% | 1 | 1 | 0% | 3,112 | 1,304 | -58% | 0 | 0 | — |
▸case-18 In graph-coloring simplification, when all remaining uncolored nodes in the interference graph have K or more neighbors, how does the allocator choose which candidate node to spill to memory? | fail→pass | 14,328 | 16,147 | +13% | 1 | 1 | 0% | 2,066 | 3,111 | +51% | 0 | 0 | — |
▸case-19 When attempting to coalesce a virtual register node with a pre-colored physical register node (such as the return register %rax), what condition must be satisfied to safely merge them without risking graph uncolorability? | pass→pass | 10,794 | 12,359 | +14% | 1 | 1 | 0% | 1,962 | 2,283 | +16% | 0 | 0 | — |
▸case-20 We are writing an instruction scheduling pass for an out-of-order x86-64 compiler backend. How should pipeline hazard latencies and instruction dependencies be represented in a Directed Acyclic Graph (DAG) to reorder instructions for maximum instruction-level parallelism? | pass→pass | 28,501 | 26,488 | -7% | 1 | 1 | 0% | 4,501 | 4,873 | +8% | 0 | 0 | — |
▸case-21 We need to select target machine instructions from an LLVM IR selection DAG using tree pattern matching. How should a bottom-up rewrite system (BURS) choose minimal-cost target instruction sequences for complex arithmetic expression trees? | pass→pass | 22,826 | 32,062 | +40% | 1 | 1 | 0% | 3,694 | 5,386 | +46% | 0 | 0 | — |
▸case-22 Our C++ backend needs to establish stack frame layouts and emit DWARF Call Frame Information (.cfi_def_cfa, .cfi_offset) for stack unwinding during exception handling. What steps determine frame pointer offsets for local variables and saved registers? | pass→pass | 21,291 | 22,596 | +6% | 1 | 1 | 0% | 3,830 | 4,790 | +25% | 0 | 0 | — |
▸case-23 We are building a dominance-based Dead Code Elimination pass operating on SSA form IR. How should the pass identify and remove instructions that have no side effects and whose outputs are never consumed? | pass→pass | 19,296 | 23,607 | +22% | 1 | 1 | 0% | 3,268 | 3,788 | +16% | 0 | 0 | — |