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Expert skill for developing and validating timing constraints. Writes SDC (Synopsys Design Constraints) and XDC files for FPGA timing closure.
Passed 20 of 23 test cases with the skill, and 14 of 23 without it.
and 10 more in the full report
7 fixed13 passed either way2 still failing1 broke
Tokens, turns and time describe resource use, not a dollar price.
One of 7 test cases the skill fixed. Same model, same prompt, with and without the skill.
When constraining a timing path between two phase-shifted clocks `clk_0` and `clk_90` where the source clock leads the destination clock by 90 degrees (quarter period), write the XDC TCL set_multicycle_path command for setup specifying that the launch edge is moved back by 1 cycle.
| Checked | Without skill | With skill |
|---|---|---|
| The set_multicycle_path command uses the -start flag. | Passed | Passed |
| The setup value in the set_multicycle_path command is 1. | Missed | Passed |
The instructions your model reads when the skill loads.
Expert skill for FPGA timing constraint development following SDC (Synopsys Design Constraints) and Xilinx XDC standards. Provides deep expertise in clock definition, I/O timing, false paths, multicycle paths, and constraint validation.
The Timing Constraints skill enables comprehensive timing constraint development for FPGA designs, supporting:
Define primary clocks entering the FPGA:
# Primary clock on input pin
create_clock -name sys_clk -period 10.000 [get_ports clk_100mhz]
# Clock with duty cycle specification
create_clock -name sys_clk -period 10.000 -waveform {0 5} [get_ports clk_100mhz]
# Multiple primary clocks
create_clock -name clk_a -period 8.000 [get_ports clk_125mhz]
create_clock -name clk_b -period 6.667 [get_ports clk_150mhz]
# Clock on GT/transceiver reference
create_clock -name gt_refclk -period 6.400 [get_ports gt_refclk_p]
# Virtual clock (for I/O timing without physical pin)
create_clock -name virt_clk -period 10.000
test cases passed, vs 14 / 23 without
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