▸case-03 I am building a bare-metal I2C master driver for an ARM Cortex-M micro-controller without relying on heavy vendor libraries. Can you generate a complete, compilable register-level driver including initialization, non-blocking transfer functions, flag status handling inside the ISR, and an example showing how to perform a read transaction? Include explanatory notes on status register handling and safety considerations. | fail→pass | 34,305 | 43,112 | +26% | 1 | 1 | 0% | 8,267 | 8,626 | +4% | 0 | 0 | — |
▸case-01 I am developing a high-speed sensor interface on an STM32H7 microcontroller. Could you write a complete, compilable C driver for the SPI peripheral using DMA transfers? Please include the peripheral initialization, interrupt service routine routines, DMA buffer configuration, and an example showing how to trigger and wait for a transaction safely without memory issues. | pass→pass | 30,085 | 33,848 | +13% | 1 | 1 | 0% | 6,841 | 7,886 | +15% | 0 | 0 | — |
▸case-02 I need to implement a robust UART receiver driver with a circular ring buffer for a Teensy 4.1 platform running at high baud rates. Please provide a production-ready, fully compilable software driver module including initialization, the receive ISR, and non-blocking read functions, along with clear documentation explaining how thread safety and CPU cache coherency are handled. | fail→pass | 49,639 | 49,559 | -0% | 1 | 1 | 0% | 8,261 | 9,263 | +12% | 0 | 0 | — |
▸case-04 I'm configuring a timer interrupt on an i.MX RT1062 chip to toggle a GPIO. However, the interrupt fires repeatedly even after I clear the interrupt flag at the start of the ISR. I tried adding simple delay loops but the issue persists. What hardware mechanism causes this and how should the ISR code structure fix it? | pass→pass | 13,640 | 18,247 | +34% | 1 | 1 | 0% | 2,445 | 4,409 | +80% | 0 | 0 | — |
▸case-05 I configured an ADC DMA transfer into a RAM buffer on an STM32F7, but the CPU keeps reading stale zero values even though the transfer complete interrupt fired. Should I disable the CPU cache globally to fix this? | pass→pass | 13,150 | 14,348 | +9% | 1 | 1 | 0% | 2,567 | 3,949 | +54% | 0 | 0 | — |
▸case-06 When clearing a status flag in a peripheral interrupt register on an SAMD51, I am using a bitwise AND assignment `STATUS &= ~FLAG_MASK;` to ensure I don't touch other flags. Is this the standard safe approach for bit clearing on Cortex-M peripherals? | pass→pass | 12,909 | 16,059 | +24% | 1 | 1 | 0% | 2,446 | 3,667 | +50% | 0 | 0 | — |
▸case-07 In an embedded Rust application for an nRF52840, I need to share a UART driver peripheral between the main loop and an interrupt handler. I plan to store it in a `static mut UART: Option<UartDriver> = None;` and wrap accesses in `unsafe` blocks. What pattern should I use instead? | pass→pass | 14,911 | 16,768 | +12% | 1 | 1 | 0% | 2,882 | 4,436 | +54% | 0 | 0 | — |
▸case-08 I am sending data from an SPI interrupt handler to a FreeRTOS worker task on Cortex-M4. Should I call `xQueueSend()` inside the ISR or perform task notification directly? | pass→pass | 13,773 | 15,953 | +16% | 1 | 1 | 0% | 2,555 | 4,121 | +61% | 0 | 0 | — |
▸case-09 I need a non-blocking microsecond delay check using the SysTick register `SysTick->VAL` on an STM32F4. I plan to read `SysTick->VAL` at start and subtract it from current `SysTick->VAL` to compute elapsed ticks. Will this work robustly? | pass→pass | 18,731 | 18,527 | -1% | 1 | 1 | 0% | 3,435 | 4,426 | +29% | 0 | 0 | — |
▸case-10 When modifying MPU region configurations on an ARM Cortex-M7 at runtime, my MCU triggers an unpredictable HardFault on subsequent instruction execution. I already updated the MPU registers in sequence. What instruction sequence am I missing? | fail→fail | 14,395 | 13,642 | -5% | 1 | 1 | 0% | 2,128 | 3,652 | +72% | 0 | 0 | — |
▸case-11 I am sampling analog sensors using SAADC on nRF52832 with EasyDMA enabled. I allocated the sample buffer inside a local function on the stack. The DMA transfers seem to corrupt stack frame pointers. What is the rule for DMA buffers on nRF52? | pass→pass | 15,764 | 18,168 | +15% | 1 | 1 | 0% | 2,577 | 4,114 | +60% | 0 | 0 | — |
▸case-12 I am setting up an external interrupt line on SAMD21 for a mechanical push button using register access. The interrupt triggers multiple times per press due to contact bounce. Can software filtering or register setup fix this inside the EIC driver? | pass→pass | 19,848 | 25,613 | +29% | 1 | 1 | 0% | 3,648 | 5,548 | +52% | 0 | 0 | — |
▸case-13 Inside a Zephyr RTOS GPIO callback function for an ARM Cortex-M board, I need to perform a 10ms I2C sensor read loop. Can I call `k_msleep(10)` inside this callback? | pass→pass | 12,008 | 13,924 | +16% | 1 | 1 | 0% | 2,200 | 3,704 | +68% | 0 | 0 | — |
▸case-14 My STM32 USB CDC device drops packets when sending telemetry data every 1ms using `CDC_Transmit_FS()`. The function returns `USBD_BUSY` frequently. How should packet queuing be handled for high-throughput USB CDC? | pass→pass | 23,132 | 31,157 | +35% | 1 | 1 | 0% | 4,155 | 7,158 | +72% | 0 | 0 | — |
▸case-20 I am writing a Linux kernel platform driver in C for a PCIe network card on an ARM64 (Aarch64) server processor. Can you provide the `probe()` and `remove()` functions using `pci_register_driver`? | pass→pass | 24,864 | 26,341 | +6% | 1 | 1 | 0% | 4,761 | 6,448 | +35% | 0 | 0 | — |
▸case-15 I have an STM32F4 application with FreeRTOS. Interrupts assigned to priority 0 are causing system crashes when calling FreeRTOS API functions. I set `configMAX_SYSCALL_INTERRUPT_PRIORITY` to 5. What is the root cause? | pass→pass | 12,450 | 16,599 | +33% | 1 | 1 | 0% | 2,030 | 3,496 | +72% | 0 | 0 | — |
▸case-16 My Cortex-M4 MCU enters the `HardFault_Handler`. I want to write C code inside the fault handler to extract the stacked Program Counter (PC) and Link Register (LR) at the moment of the fault. How do I reliably retrieve the correct stack pointer frame? | pass→pass | 21,845 | 43,729 | +100% | 1 | 1 | 0% | 3,815 | 8,512 | +123% | 0 | 0 | — |
▸case-17 I am configuring FlexCAN on i.MX RT1062 for CAN 2.0B extended IDs (29-bit). I set the filter register but all standard ID messages are passing through. How should extended ID filter bit shifting be applied in FlexCAN MB registers? | pass→pass | 34,773 | 30,183 | -13% | 1 | 1 | 0% | 5,461 | 7,087 | +30% | 0 | 0 | — |
▸case-18 I am porting bit-banding register manipulation code from Cortex-M3 to SAMD20 (Cortex-M0+). The compiler throws an error accessing bit-band alias memory addresses. How should atomic bit updates be handled on Cortex-M0+? | pass→pass | 16,919 | 17,455 | +3% | 1 | 1 | 0% | 2,703 | 4,508 | +67% | 0 | 0 | — |
▸case-19 After jumping from a custom bootloader to the main firmware application at address `0x08008000` on an ARM Cortex-M4, interrupts trigger vectors in the bootloader instead of application handlers. What vector register must be updated upon application startup? | pass→pass | 6,334 | 11,450 | +81% | 1 | 1 | 0% | 1,134 | 2,876 | +154% | 0 | 0 | — |
▸case-21 I am designing a custom SPI master controller on a Xilinx Artix-7 FPGA using VHDL. Can you write the state machine logic in VHDL for SCLK generation and shift register operation? | pass→pass | 38,995 | 30,167 | -23% | 1 | 1 | 0% | 7,331 | 5,765 | -21% | 0 | 0 | — |
▸case-22 I am routing a 4-layer PCB in KiCad for an STM32H7 board. What trace impedance rules and layer stackup guidelines should I apply for 480 Mbps High-Speed USB differential pairs? | pass→pass | 21,813 | 23,010 | +5% | 1 | 1 | 0% | 3,765 | 5,140 | +37% | 0 | 0 | — |