HSB IP Create Top Skill

HSB IP Create Top Skill

Purpose

Create a fixed-format SystemVerilog top-level scaffold that instantiates HOLOLINK_top and declares the HSB-facing signals required by a validated HOLOLINK_def.svh.

This skill owns only the top-level scaffold around the HSB IP:

• SPDX/Apache license header
• HOLOLINK_def.svh include
• FPGA_top module shell
• HSB-facing signal declarations
• HOLOLINK_top instantiation
• comments/TODOs for top-level integration

Use hsb-ip-def for HOLOLINK_def.svh generation and validation. Do not create or validate the defs file here.

Prerequisites

• A validated HOLOLINK_def.svh path or pasted file content is required before generating FPGA_top.sv.
• Live HOLOLINK_top.sv source is preferred when source-sensitive port extraction is needed; bundled references cover known rev 16'h2604 and compatible rev 16'h2603.
• The user must provide or accept the output path when writing a scaffold file.

Instructions

• Require a validated HOLOLINK_def.svh before creating FPGA_top.sv. If the user does not have one, invoke or direct them to hsb-ip-def first.
• Treat live HOLOLINK_top.sv as the source of truth for ports, directions, macro gates, and IP revision whenever it is available.
• First classify the request as Standalone Create Top, Def-Skill Handoff, or Explain. Load only the references required for that workflow and do not re-read the same reference just to reconfirm formatting.
• Use references/fixed-format.md as the baked formatting and naming style. Do not inspect example top-level files just to confirm formatting during normal generation.
• Emit a fixed-format scaffold, not a complete project top. Because the surrounding design is unknown, the generated FPGA_top module normally has no top-level ports.
• Derive active signal groups from the validated defs file. Do not connect ports that are absent from HOLOLINK_top under the active macro set.
• Preserve HOLOLINK_top port shapes exactly: keep packed vector widths before the signal name and unpacked interface-array dimensions after the signal name.
• When using bundled known-rev references, still preserve the signal shapes in references/fixed-format.md, including unpacked arrays for multi-interface *_tdata, *_tkeep, and *_tuser buses and the APB shape documented there.
• Use sensor-agnostic language. Say "sensor data", "sensor interface", and "stream"; use camera-specific language only after the user says the design is camera-specific.
• Ask one plain-language question per turn when information is missing. Keep source-selection questions as plain-language prompts rather than radio buttons, structured choices, or multi-question prompts.
• Do not invent project-specific integration details. Leave concise TODO comments where the surrounding design must connect to HSB.
• For packetizer comments in FPGA_top.sv, use generic wording such as "data manipulation behavior".
• In final summaries, include the defs validation/source status, the port-map source used, and the emitted HSB signal groups. Do not enumerate what is outside the scaffold's scope. Use only this generic note: "This file is a reference/template for hooking up top-level signals and companion IP to the HSB IP."

Live HSB IP Source Policy