▸case-01 An STM32L4 application needs to sleep for 5 seconds between sensor readings, preserving all SRAM content and register state while keeping current consumption under 2 uA. A developer suggests using Standby mode to get the lowest current. Which low-power mode should be selected instead? | pass→pass | 6,745 | 9,934 | +47% | 1 | 1 | 0% | 1,303 | 1,603 | +23% | 0 | 0 | — |
▸case-02 A GPIO interrupt service routine fires at 10 kHz on an ARM Cortex-M4 running FreeRTOS. To process the data, the developer writes the entire processing logic inside the ISR directly. What FreeRTOS pattern should be used to defer this work to a task? | pass→pass | 9,462 | 7,763 | -18% | 1 | 1 | 0% | 1,782 | 1,510 | -15% | 0 | 0 | — |
▸case-03 An ESP32 battery node enters Deep Sleep between MQTT posts. Variables tracking boot count need to survive across wake cycles without writing to flash NVS due to wear concerns. Where should these variables be allocated in memory? | pass→pass | 8,273 | 7,672 | -7% | 1 | 1 | 0% | 1,451 | 1,519 | +5% | 0 | 0 | — |
▸case-04 An embedded UART receiver running at 921600 baud experiences overrun errors during high CPU load when using single-byte interrupts. What hardware feature combination should be configured to buffer incoming bytes autonomously? | pass→pass | 10,367 | 8,748 | -16% | 1 | 1 | 0% | 1,658 | 1,552 | -6% | 0 | 0 | — |
▸case-05 A bare-metal C program polls a hardware status register flag in a while loop: `while (!(STATUS_REG & READY_BIT));`. The compiler optimization is set to -O3, and the loop hangs indefinitely because the status register is cached in a CPU register. How must STATUS_REG pointer be declared? | pass→pass | 4,245 | 5,326 | +25% | 1 | 1 | 0% | 843 | 1,161 | +38% | 0 | 0 | — |
▸case-06 An I2C bus operating at Fast-Mode (400 kHz) with 100 pF bus capacitance is failing signal rise-time specs when using standard 10k ohm pull-up resistors. What resistor value range should replace the 10k resistors? | pass→pass | 13,987 | 11,860 | -15% | 1 | 1 | 0% | 2,548 | 2,994 | +18% | 0 | 0 | — |
▸case-07 A flash memory IC datasheet specifies that data is sampled on the leading rising edge of SCK and shifted out on the trailing falling edge, with SCK idling low when inactive. Which SPI mode (0, 1, 2, or 3) must be configured? | pass→pass | 4,974 | 4,647 | -7% | 1 | 1 | 0% | 1,165 | 1,169 | +0% | 0 | 0 | — |
▸case-08 A developer attempts to push an incoming data byte to a FreeRTOS queue inside a hardware ISR using `xQueueSend()`. The program crashes with an assertion failure. Which API function must be called inside the interrupt handler? | pass→pass | 3,056 | 4,677 | +53% | 1 | 1 | 0% | 563 | 957 | +70% | 0 | 0 | — |
▸case-09 An ESP32 application runs heavy DSP math on Task A, causing WiFi stack dropouts because both run on Core 0 by default. How should Task A be created to prevent starving the WiFi protocol task on Core 0? | pass→pass | 11,524 | 8,955 | -22% | 1 | 1 | 0% | 2,180 | 1,852 | -15% | 0 | 0 | — |
▸case-10 An STM32 ADC measuring a high-impedance (200k ohm) temperature sensor reads values 15% lower than actual voltage when using a short sampling time of 2.5 clock cycles. What ADC parameter must be adjusted to fix the loading effect? | pass→pass | 7,175 | 7,981 | +11% | 1 | 1 | 0% | 1,223 | 1,607 | +31% | 0 | 0 | — |
▸case-11 A complementary MOSFET half-bridge driver is controlled by two PWM channels. During switching transitions, a brief shoot-through short circuit occurs across the DC bus. What timer peripheral configuration prevents this condition? | pass→pass | 8,127 | 6,474 | -20% | 1 | 1 | 0% | 1,421 | 1,274 | -10% | 0 | 0 | — |
▸case-12 A safety-critical system uses a Window Watchdog (WWDG). A junior developer adds `refresh_watchdog()` calls at the very beginning of the main loop, causing immediate micro resets. Why does refreshing early cause a reset? | pass→pass | 12,920 | 11,205 | -13% | 1 | 1 | 0% | 1,547 | 1,785 | +15% | 0 | 0 | — |
▸case-13 A battery-powered FreeRTOS device spends 95% of its time waiting on queue timeouts, but tick interrupts fire every 1 ms, keeping the CPU awake. What FreeRTOS feature suspends the periodic tick interrupt during idle periods? | fail→pass | 3,194 | 6,121 | +92% | 1 | 1 | 0% | 508 | 1,255 | +147% | 0 | 0 | — |
▸case-14 A push-button connected to a GPIO interrupt triggers 5 to 10 false trigger events per physical press due to mechanical contact bounce. A developer suggests placing a delay loop inside the ISR. What software approach should be used instead? | pass→pass | 12,884 | 10,427 | -19% | 1 | 1 | 0% | 2,071 | 2,013 | -3% | 0 | 0 | — |
▸case-15 A multi-threaded Cortex-M3 application modifies a shared 32-bit register flag using `FLAGS |= (1 << 3);` in a task while an ISR clears bits in the same register. This causes intermittent lost bit updates. How should this bit modification be performed atomically without disabling interrupts? | pass→pass | 12,529 | 13,221 | +6% | 1 | 1 | 0% | 2,406 | 2,968 | +23% | 0 | 0 | — |
▸case-16 An embedded device updates an operating configuration counter in raw flash sectors every minute. After 3 months in the field, flash writes start failing. What storage management pattern prevents premature single-sector flash degradation? | fail→fail | 10,244 | 11,776 | +15% | 1 | 1 | 0% | 1,683 | 2,224 | +32% | 0 | 0 | — |
▸case-17 An STM32F4 clocked at 168 MHz from an 8 MHz crystal needs to enable the USB OTG FS peripheral. The USB hardware fails to enumerate because the USB clock is out of specification. What clock system output frequency must be configured for the USB domain? | pass→pass | 8,380 | 8,698 | +4% | 1 | 1 | 0% | 1,339 | 1,978 | +48% | 0 | 0 | — |
▸case-18 In an ARM Cortex-M system, NVIC Priority Grouping is set so all bits are subpriority bits (0 preemption bits). A high-priority sensor ISR is delayed while a long low-priority communication ISR runs. How must NVIC priority grouping be configured so high-priority ISRs interrupt low-priority ones? | pass→pass | 9,272 | 7,563 | -18% | 1 | 1 | 0% | 1,727 | 1,606 | -7% | 0 | 0 | — |
▸case-19 An ESP-IDF application needs to enter Light Sleep mode and automatically resume execution on a rising edge on GPIO 34 without executing a full chip reset. Which wakeup source API must be configured prior to sleeping? | pass→pass | 12,376 | 9,817 | -21% | 1 | 1 | 0% | 2,512 | 2,099 | -16% | 0 | 0 | — |
▸case-20 A hardware engineer is laying out a 4-layer PCB for USB 2.0 High-Speed signals. What differential trace impedance should be targeted for the DP/DM pair routing? | pass→pass | 6,834 | 6,244 | -9% | 1 | 1 | 0% | 936 | 1,282 | +37% | 0 | 0 | — |
▸case-21 A Linux kernel driver developer is writing a character device module for an x86 host. What kernel structure registers the `read`, `write`, `open`, and `release` callback pointers? | pass→pass | 4,689 | 4,440 | -5% | 1 | 1 | 0% | 842 | 979 | +16% | 0 | 0 | — |
▸case-22 A VHDL designer is implementing a synchronous flip-flop process on a Xilinx Artix-7 FPGA. Which signals must be present in the process sensitivity list for a synchronous clock with asynchronous active-low reset? | pass→pass | 6,412 | 6,780 | +6% | 1 | 1 | 0% | 1,141 | 1,346 | +18% | 0 | 0 | — |