▸case-01 We are setting up an embedded C project generated by CubeMX and adding application logic with RTOS tasks. Could you review our approach and provide guidelines on how to structure our application logic separately from vendor-generated files, manage hardware abstraction layers safely, and handle peripheral error checking without blocking the execution path? | fail→pass | 18,953 | 19,247 | +2% | 1 | 1 | 0% | 3,418 | 4,015 | +17% | 0 | 0 | — |
▸case-02 In our STM32 bare-metal driver, we use `volatile int delay_cnt;` inside a software delay loop to prevent compiler optimization, and we also use `volatile` for a local variable in a processing function. Is this appropriate memory keyword usage for embedded C? | pass→pass | 14,409 | 10,884 | -24% | 1 | 1 | 0% | 2,406 | 2,461 | +2% | 0 | 0 | — |
▸case-03 We are designing an STM32 microcontroller application handling variable-length telemetry packets over UART. To save static RAM, our team plans to allocate buffers dynamically using malloc() and free() on the heap inside incoming packet handlers. What firmware memory management practice should we adopt instead? | pass→pass | 14,962 | 11,044 | -26% | 1 | 1 | 0% | 2,413 | 2,503 | +4% | 0 | 0 | — |
▸case-04 We have a 1024-element 16-bit sine lookup table in our motor control firmware for STM32, currently declared as `uint16_t sin_table[1024] = { ... };`. It is consuming valuable SRAM. How should this array be declared so it stays in flash memory? | pass→pass | 7,648 | 6,619 | -13% | 1 | 1 | 0% | 1,323 | 1,751 | +32% | 0 | 0 | — |
▸case-05 Our team is writing a custom SPI device driver for STM32 and using standard C types like `unsigned int` and `long` for peripheral registers and bitfield definitions. Is this suitable for bare-metal MCU hardware interfaces? | pass→pass | 17,471 | 15,297 | -12% | 1 | 1 | 0% | 3,176 | 3,468 | +9% | 0 | 0 | — |
▸case-06 Our STM32 timer ISR handles sensor data acquisition. Inside the ISR, we process the 256-sample buffer using an inline floating-point FFT and print the result over UART HAL calls. How should this interrupt routine be restructured? | pass→pass | 15,835 | 14,108 | -11% | 1 | 1 | 0% | 2,654 | 3,119 | +18% | 0 | 0 | — |
▸case-07 To handle incoming SPI frames of unknown size inside an STM32 SPI interrupt service routine, our code calls malloc() to create a packet buffer on the fly. How should memory allocation be handled in this interrupt path? | pass→pass | 14,589 | 12,854 | -12% | 1 | 1 | 0% | 2,446 | 2,597 | +6% | 0 | 0 | — |
▸case-08 We configured high-speed DMA to stream UART data into a circular SRAM buffer on STM32. Our application task reads the buffer pointers directly while DMA is transferring. Occasionally we read corrupted or stale data. What synchronization practice are we missing? | fail→fail | 16,058 | 12,061 | -25% | 1 | 1 | 0% | 2,742 | 2,739 | -0% | 0 | 0 | — |
▸case-09 In an STM32 I2C driver, we wait for the bus busy flag to clear using a tight loop `while (I2C1->ISR & I2C_ISR_BUSY);`. During hardware noise, the code occasionally hangs forever. How should wait loops be implemented? | pass→pass | 21,791 | 10,658 | -51% | 1 | 1 | 0% | 2,314 | 2,502 | +8% | 0 | 0 | — |
▸case-10 Our team is almost finished with an STM32 MCU product and wants to add an Independent Watchdog (IWDG) as a final patch by kicking it in a high-frequency hardware timer ISR. How should watchdog architecture be incorporated into firmware design? | fail→pass | 16,994 | 14,150 | -17% | 1 | 1 | 0% | 2,827 | 3,035 | +7% | 0 | 0 | — |
▸case-11 We are developing state-machine firmware for an STM32-based medical device. To test business logic, developers build the binary and flash it onto target hardware for every test run. How can unit testing be improved for faster iteration? | pass→pass | 16,464 | 22,034 | +34% | 1 | 1 | 0% | 2,817 | 3,783 | +34% | 0 | 0 | — |
▸case-12 After waking our STM32 MCU from STOP low-power mode, our code immediately attempts UART communications using existing peripheral register states without re-initialization. Why might this cause communication failures? | fail→pass | 16,003 | 12,508 | -22% | 1 | 1 | 0% | 2,524 | 2,603 | +3% | 0 | 0 | — |
▸case-13 When an STM32 HardFault occurs, our default firmware handler executes a simple `while(1);` loop, requiring a manual reset and leaving no debugging info. How should fault handlers be designed for diagnostic usefulness? | fail→pass | 23,264 | 18,409 | -21% | 1 | 1 | 0% | 3,578 | 4,098 | +15% | 0 | 0 | — |
▸case-14 A multi-byte sensor state structure is updated by an EXTI ISR on STM32 and read by an RTOS task in the main loop. Currently, the task reads the structure directly without protection. What concurrency protection should be added? | pass→pass | 15,302 | 12,071 | -21% | 1 | 1 | 0% | 2,285 | 2,663 | +17% | 0 | 0 | — |
▸case-15 When updating STM32 CubeMX configuration files, our custom modifications inside `main.c` keep getting overwritten by CubeMX code generation. How should hand-written application code be organized relative to vendor generated code? | pass→pass | 13,751 | 11,456 | -17% | 1 | 1 | 0% | 2,589 | 2,658 | +3% | 0 | 0 | — |
▸case-16 Our thermal control loop application directly calls `HAL_ADC_GetValue(&hadc1)` and `HAL_GPIO_WritePin(...)` throughout its PID calculations. This makes host unit testing impossible. How should hardware calls be abstracted? | pass→pass | 18,779 | 17,578 | -6% | 1 | 1 | 0% | 3,428 | 4,043 | +18% | 0 | 0 | — |
▸case-17 In our firmware project, multiple modules call peripheral init functions like `HAL_SPI_Init(&hspi1)` whenever they perform a transaction. What problem does this cause and how should peripheral initialization be handled? | pass→pass | 14,011 | 15,143 | +8% | 1 | 1 | 0% | 2,371 | 2,734 | +15% | 0 | 0 | — |
▸case-18 We are seeing sporadic random memory corruption in an STM32 FreeRTOS application with multiple tasks and nested interrupts. How should stack allocation and usage be monitored in embedded C? | pass→pass | 25,003 | 18,561 | -26% | 1 | 1 | 0% | 3,709 | 3,817 | +3% | 0 | 0 | — |
▸case-19 We need to process a continuous 2 Mbaud UART telemetry stream on an STM32 microcontroller. Using polling or byte-by-byte interrupts is dropping characters due to CPU overhead. What hardware transfer mechanism should be used instead? | pass→pass | 9,164 | 12,210 | +33% | 1 | 1 | 0% | 1,733 | 2,764 | +59% | 0 | 0 | — |
▸case-20 During debugging of our STM32 motor driver, the motor hardware occasionally reaches invalid states without triggering any warnings or halts. What programming practice should be added to catch invalid hardware states in debug builds? | pass→pass | 12,774 | 7,893 | -38% | 1 | 1 | 0% | 2,236 | 2,038 | -9% | 0 | 0 | — |
▸case-21 Our STM32 firmware outputs diagnostic log messages over a serial port inside high-frequency sensor acquisition loops, causing significant timing delays. How should logging and tracing be managed in production embedded code? | fail→pass | 17,635 | 20,520 | +16% | 1 | 1 | 0% | 2,940 | 3,491 | +19% | 0 | 0 | — |
▸case-22 We are setting up a central documentation file for a new STM32 hardware board project. What key low-level hardware configuration details should be explicitly documented for the firmware team? | fail→pass | 27,221 | 16,236 | -40% | 1 | 1 | 0% | 2,829 | 3,155 | +12% | 0 | 0 | — |
▸case-23 We are writing a Linux kernel character device driver for a PCI Express FPGA card on x86_64 Linux. Should we structure device file operations using copy_to_user() and sysfs attributes, or should we use STM32 HAL peripheral drivers? | pass→pass | 14,397 | 8,159 | -43% | 1 | 1 | 0% | 2,417 | 2,141 | -11% | 0 | 0 | — |
▸case-24 We are designing a custom UART IP block in SystemVerilog for a Xilinx Artix-7 FPGA. How do we configure clock enable logic and register transfer level (RTL) sensitivity lists in Verilog? | pass→pass | 18,123 | 20,187 | +11% | 1 | 1 | 0% | 3,694 | 4,521 | +22% | 0 | 0 | — |
▸case-25 We are creating a cross-platform C++ desktop GUI application using Qt 6 for visualizing telemetry data on Windows and macOS. How should we implement QAbstractTableModel and handle signal/slot connections across QThread boundaries? | pass→pass | 22,459 | 19,974 | -11% | 1 | 1 | 0% | 4,150 | 4,740 | +14% | 0 | 0 | — |