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Autonomous design space exploration loop for computer architecture and EDA. Runs a program, analyzes results, tunes parameters, and iterates until objective is met or timeout.
Passed 13 of 19 test cases with the skill, and 10 of 19 without it.
and 5 more in the full report
7 fixed10 passed either way5 still failing2 broke
Tokens, turns and time describe resource use, not a dollar price.
One of 6 test cases the skill fixed. Same model, same prompt, with and without the skill.
Where should configuration files generated for individual trial runs during design space exploration be archived?
| Checked | Without skill | With skill |
|---|---|---|
| Saves individual run configuration files under dse_results/configs/ | Missed | Passed |
The instructions your model reads when the skill loads.
Autonomously explore a design space: run → analyze → pick next parameters → repeat, until the objective is met or timeout is reached. Designed for computer architecture and EDA problems.
NEVER do any of the following:
sudo anythingrm -rf, rm -r, or any recursive deletionrm any file you did not create in this sessiongit push, git reset --hard, or any destructive git operationIf a step requires any of the above, STOP and report to the user.
| Constant | Default | Description |
|---|---|---|
TIMEOUT | 2h | Total wall-clock budget. Stop exploring after this. |
MAX_ITERATIONS | 50 | Hard cap on number of design points evaluated. |
PATIENCE | 10 | Stop early if no improvement for this many consecutive iterations. |
OBJECTIVE | minimize | minimize or maximize the target metric. |
Override inline: /dse-loop "task desc — timeout: 4h, max_iterations: 100, patience: 15"
| Problem | Program | Parameters | Objective |
|---|---|---|---|
| Microarch DSE | gem5 simulation | cache size, assoc, pipeline width, ROB size, branch predictor | maximize IPC or minimize area×delay |
| Synthesis tuning | yosys/DC script | optimization passes, target freq, effort level | minimize area at timing closure |
| RTL parameterization | verilator sim | data width, FIFO depth, pipeline stages, buffer sizes | meet throughput target at min area |
| Compiler flags | gcc/llvm build + benchmark | -O levels, unroll factor, vectorization, scheduling | minimize runtime or code size |
| Placement/routing | openroad/innovus | utilization, aspect ratio, layer config | minimize wirelength / timing |
| Formal verification | abc/sby | bound depth, engine, timeout per property | maximize coverage in time budget |
| Memory subsystem | cacti / ramulator | bank count, row buffer policy, scheduling | optimize bandwidth/energy |
test cases passed, vs 10 / 19 without
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