Use when designing a Digital Down Converter (DDC) using dsphdl System objects. Triggers on requests involving DDC design, frequency down-conversion for FPGA/ASIC, NCO + mixer + decimation filter chains, fractional/non-integer sample rate conversion, or HDL-optimized receiver front-end signal processing.
SkillScore82Maintained
Automatic
◆Coding pack
Last verified 8/16/2026
What it changes
Passed 18 of 22 test cases with the skill, and 10 of 22 without it.
Without skill45%
With skill82%
Checks it passed that the model alone missed
Calculates the phase increment as a negative integer value
Sets RateChange as input sample rate divided by output sample rate
Specifies the multiplication without applying conj to the NCO output
and 12 more in the full report
10 fixed8 passed either way2 still failing2 broke
Pass-rate lift
+36 pp
Tokens
+167%
Agent turns
0%
Response time
-59%
Model gemini-3.6-flashMeasured 8/16/2026v118 of 22 cases passed with skill
Tokens, turns and time describe resource use, not a dollar price.
See it in action
One of 10 test cases the skill fixed. Same model, same prompt, with and without the skill.
1 of 10
Prompt
I'm building a receiver front-end where the output sample rate is not an exact integer fraction of the input sample rate. I want to construct an HDL-optimized DDC in MATLAB using `dsphdl` objects that handles fractional decimation. Please interactively ask me for the necessary design specifications one step at a time, then generate the design script, the top-level persistent function wrapper supporting streaming data and valid flags, a testbench that plots I/Q and PSD, and the commands to run HDL Coder.
What was checked, without and with the skill
Checked
Without skill
With skill
Prompts with exactly one question at a time to collect design parameters interactively
Passed
Passed
Asks for input sampling frequency and carrier frequency in the first question
Missed
Passed
case-02 · gemini-3.6-flash · 8/16/2026 · answers are capped and redacted
What's inside
The instructions your model reads when the skill loads.
SKILL.md456 lines4 files
dsphdl DDC: Design, Simulate, Generate HDL
Overview
End-to-end MATLAB workflow for designing a Digital Down Converter (DDC) using dsphdl System objects — combining an NCO (local oscillator), complex mixer, and multi-stage decimation filter chain — then simulating the streaming HDL-optimized design and generating synthesizable HDL via HDL Coder.
Integer decimation (all stages have integer rate change):
RF Input → [Mixer] → [CIC Decimator] → [Compensation FIR Decimator] → Baseband Output
↑
[NCO] (generates cos + jsin at carrier frequency)
Non-integer decimation (uses Farrow for fine rate adjustment):
RF Input → [Mixer] → [CIC Dec (xR)] → [Farrow (L/M)] → [FIR Dec (xD)] → Baseband Output
↑
[NCO]
When to Use
Designing a DDC or receiver front-end for FPGA/ASIC
Building an NCO + mixer + decimation chain with dsphdl objects
Non-integer decimation — when the target output rate doesn't divide evenly into the input rate
Converting a floating-point DDC algorithm to HDL-ready streaming architecture
Generating Verilog/VHDL for a complete DDC subsystem
When Not To Use
Non-HDL workflows, e.g. embedded C code generation
Critical Conventions
NCO Phase Increment
ALWAYS compute as:phaseInc = round((-Fc * 2^AccumulatorWL) / Fs) where Fc is the carrier frequency, Fs is the input sample frequency, and AccumulatorWL is the NCO accumulator word length. This produces a negative integer. Never omit the negation or compute round(Fc / Fs * 2^AccumulatorWL) — the negative sign is required for correct down-conversion.
Mixer: direct multiply with fi() arithmetic — NO conjugate