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Per-controller PCIe enable / disable / lanes / link-speed for a Jetson Thor or Orin custom carrier via ODMDATA + kernel-DT overlay.
Passed 13 of 18 test cases with the skill, and 5 of 18 without it.
and 13 more in the full report
11 fixed5 passed either way5 still failing1 broke
Tokens, turns and time describe resource use, not a dollar price.
One of 10 test cases the skill fixed. Same model, same prompt, with and without the skill.
An operator wants to configure PCIe controller C0 as an Endpoint (EP) instead of Root Complex (RC) on Jetson Thor. What parameter must be passed during the plan derivation step to emit an endpoint node fragment?
| Checked | Without skill | With skill |
|---|---|---|
| Requires `mode_override="ep"` to emit an endpoint overlay fragment. | Missed | Passed |
The instructions your model reads when the skill loads.
PCIe on Tegra264 (Thor, [email protected]) and Tegra234 (Orin,
[email protected]) is split across multiple controllers that share the
UPHY lane pool with USB3 / MGBE / UFS. Each controller's runtime
behavior is determined by two surfaces, both required:
| Surface | Target | Authoritative for |
|---|---|---|
ODMDATA pcie@N_status=… (+ pcie@N_max-link-speed, pcie@N_pcie-mode, pcie@N_clk-scheme, pcie-cN-endpoint-enable) | /pcie/pcie@N in BPMP DTB | UPHY lane power, refclk gating, controller-side power rails |
Kernel-DT overlay on &pcieN | /bus@0/pcie@<addr> in kernel DTB | Kernel probe, lane width, link speed, RC/EP mode |
Skipping the kernel overlay on a disable lets the kernel probe a powered-down PHY (link timeouts in dmesg). Skipping the ODMDATA token on a disable leaves BPMP holding the PHY hot.
Agentic, not table-driven — no controller table, no
questions.json. Every controller, lane width, schematic-routed
receptacle, and authoritative DT node address is discovered at runtime
from the docs + DTB + carrier pinmap.
The output is a kernel-DT overlay commit only. Per-controller
fragment@N blocks are appended to the composite custom overlay
.dts per
../../references/bsp-customization-kernel-dtb.md
and committed to the bsp_sources/ hardware repo.
/jetson-build-source compiles the composite to .dtbo and owns its
Makefile + flash-conf registration.
This skill MUST NOT edit ODMDATA="...". All ODMDATA tokens
(pcie@N_status=…, pcie@N_max-link-speed, pcie@N_pcie-mode,
pcie@N_clk-scheme, pcie-cN-endpoint-enable, plus the
uphyX-config-N surface tokens and UPHY_CONFIG="" clear) are
emitted by /jetson-customize-uphy in a single atomic commit on the
carrier flash-conf fork. The allocation table this skill consumes
from the UPHY sidecar already tells the operator which controllers
are okay / disabled / per-lane sized; this skill only translates
that table into kernel-DT overlay fragments and verifies that the
test cases passed, vs 5 / 18 without
More skills from the same source and nearby in the registry, with their headline benchmark lift.