▸case-01 I have a C++ FIR filter kernel targeted for FPGA high-level synthesis where the main sample processing loop takes 5 clock cycles per iteration by default. I need to achieve maximum sample processing throughput so that a new input sample can be accepted every single clock cycle. Write the C++ loop code with the appropriate pragma. | pass→pass | 13,570 | 21,950 | +62% | 1 | 1 | 0% | 2,541 | 3,150 | +24% | 0 | 0 | — |
▸case-02 I am synthesizing an 8-tap parallel matrix multiplier in HLS C++. The loop accesses array B[8][8] multiple times per cycle, but synthesis reports block RAM port contention causing a high initiation interval. How should the array declaration or pragma be modified in the HLS source to allow simultaneous access to all elements? | pass→pass | 13,601 | 13,106 | -4% | 1 | 1 | 0% | 2,051 | 2,700 | +32% | 0 | 0 | — |
▸case-03 I am writing an HLS C++ top-level function process_image that accepts scalar configuration values width, height, and mode, plus a start/done block control signal. What interface pragma and mode should be assigned to these scalar arguments and top-level block control for integration into a host CPU memory map? | pass→fail | 11,737 | 10,532 | -10% | 1 | 1 | 0% | 2,191 | 2,443 | +12% | 0 | 0 | — |
▸case-04 In an HLS accelerator kernel, I need to read a 1 MB array of floating-point feature vectors from host DDR main memory via direct burst memory access. Write the function signature and HLS interface pragma for the input pointer parameter. | pass→pass | 12,609 | 7,670 | -39% | 1 | 1 | 0% | 2,178 | 1,885 | -13% | 0 | 0 | — |
▸case-05 I am designing a high-throughput network packet parser kernel in C++ for FPGA synthesis that receives sequential stream packets from an Ethernet IP core without addressing overhead. What interface mode pragma should be applied to the input stream data structure? | pass→pass | 13,985 | 8,345 | -40% | 1 | 1 | 0% | 2,332 | 2,041 | -12% | 0 | 0 | — |
▸case-06 I'm writing a C++ function for high-level synthesis that processes variable-length frame data. A software engineer suggested allocating frame buffers dynamically using std::vector<int> or malloc() based on runtime frame length. Write the HLS-compliant array definition approach for this buffer. | pass→pass | 13,259 | 16,346 | +23% | 1 | 1 | 0% | 2,670 | 3,781 | +42% | 0 | 0 | — |
▸case-07 In an HLS image processing pipeline, three sub-functions (read_pixels, filter_pixels, write_pixels) execute sequentially in a wrapper function using intermediate stream channels. How can these three sequential sub-functions be configured to run concurrently in a pipelined execution model? | pass→pass | 15,396 | 43,762 | +184% | 1 | 1 | 0% | 2,345 | 3,170 | +35% | 0 | 0 | — |
▸case-08 I am implementing a 12-bit analog sensor sample processing pipeline in HLS C++. Using standard 32-bit int types wastes DSP slices and LUT resources on the FPGA. What data types should be used in Vivado HLS for 12-bit signed and 12-bit unsigned integers? | pass→pass | 13,306 | 9,837 | -26% | 1 | 1 | 0% | 2,104 | 1,933 | -8% | 0 | 0 | — |
▸case-09 I need to perform fractional calculations in an HLS C++ kernel for a low-power FPGA. Floating-point arithmetic (float) consumes too many LUTs and DSPs. What fixed-point template type should be used to represent a signed number with 16 total bits and 4 integer bits? | pass→pass | 9,227 | 6,720 | -27% | 1 | 1 | 0% | 1,817 | 1,750 | -4% | 0 | 0 | — |
▸case-10 I have an inner loop of 16 iterations performing vector addition in an HLS kernel. I want to execute 4 vector additions in parallel per clock cycle rather than fully unrolling all 16 iterations or processing 1 per cycle. Write the HLS pragma for partial loop unrolling. | pass→pass | 9,170 | 6,047 | -34% | 1 | 1 | 0% | 1,329 | 1,306 | -2% | 0 | 0 | — |
▸case-11 I have a small HLS IP block that outputs a single scalar alert signal directly to standard FPGA logic fabric without any bus interface wrappers or control registers. What simple HLS interface mode pragma should be specified for this output port? | pass→pass | 8,470 | 7,417 | -12% | 1 | 1 | 0% | 1,478 | 1,570 | +6% | 0 | 0 | — |
▸case-12 I synthesized a baseline HLS C++ design for a matrix multiplication kernel, but the synthesis report shows an Initiation Interval (II) of 12 cycles due to loop dependencies and memory port limitations. Describe the structured multi-step optimization sequence to diagnose and fix this bottleneck. | pass→pass | 20,461 | 17,535 | -14% | 1 | 1 | 0% | 3,701 | 3,611 | -2% | 0 | 0 | — |
▸case-13 In a dataflow HLS design with hls::stream channels between functions, synthesis reports stall conditions because the producer function writes bursts faster than the consumer reads. What pragma or depth specification should be added to prevent buffer underflow or overflow in the stream channel? | pass→pass | 10,291 | 8,282 | -20% | 1 | 1 | 0% | 1,873 | 1,909 | +2% | 0 | 0 | — |
▸case-14 I have a loop in an HLS C++ design whose upper bound is a runtime scalar parameter N. Vivado HLS reports unknown latency and cannot estimate worst-case timing. What pragma allows supplying a typical or maximum iteration count hint to the synthesis tool? | pass→pass | 6,293 | 6,135 | -3% | 1 | 1 | 0% | 1,205 | 1,547 | +28% | 0 | 0 | — |
▸case-15 I have multiple scalar parameters scale, offset, and threshold in an HLS top-level function. I want all three parameters grouped into a single combined AXI4-Lite slave memory interface named BUS_A. Write the interface pragmas for these arguments. | pass→pass | 7,511 | 4,815 | -36% | 1 | 1 | 0% | 1,159 | 1,325 | +14% | 0 | 0 | — |
▸case-16 I am declaring a persistent lookup table inside an HLS C++ function that must retain its state across multiple function calls without being re-initialized every invocation. Show the C++ variable declaration for this array. | pass→pass | 8,076 | 8,435 | +4% | 1 | 1 | 0% | 1,390 | 1,636 | +18% | 0 | 0 | — |
▸case-17 I have a complex calculation block in HLS C++ that must complete within a strict latency budget of 20 clock cycles. What HLS pragma can be applied to enforce a maximum latency constraint on a region or function? | pass→pass | 10,602 | 7,755 | -27% | 1 | 1 | 0% | 1,523 | 1,799 | +18% | 0 | 0 | — |
▸case-18 I have a small helper function in HLS C++ called add_bits that is invoked millions of times inside a nested loop. The function call hierarchy overhead is introducing clock cycle latency. What HLS pragma removes the function hierarchy to eliminate call overhead? | pass→pass | 8,426 | 5,369 | -36% | 1 | 1 | 0% | 1,435 | 1,308 | -9% | 0 | 0 | — |
▸case-19 I need to access 4 consecutive elements of a 1D array in HLS C++ simultaneously, but I want to combine block RAM elements into a wider 64-bit word instead of splitting the block RAM into 4 separate single-port RAM blocks. What pragma accomplishes memory reshaping? | pass→pass | 9,920 | 8,962 | -10% | 1 | 1 | 0% | 1,830 | 2,084 | +14% | 0 | 0 | — |
▸case-20 I am designing a custom UART transmitter module in SystemVerilog for an FPGA. Write a SystemVerilog module with clk, rst_n, tx_start, tx_data[7:0], and tx output line using an explicit finite state machine. | pass→pass | 20,781 | 14,579 | -30% | 1 | 1 | 0% | 4,371 | 3,552 | -19% | 0 | 0 | — |
▸case-21 I am writing host-side C++ Linux user-space code to load an xclbin bitstream and enqueue buffer transfers to an FPGA accelerator card using the Xilinx Runtime (XRT) host API (xrt::device, xrt::bo, xrt::kernel). Show how to allocate host memory and execute the kernel from the host CPU. | pass→pass | 16,514 | 26,329 | +59% | 1 | 1 | 0% | 3,668 | 4,878 | +33% | 0 | 0 | — |
▸case-22 I need a Vivado TCL script to run implementation, place and route, and generate a timing report for a synthesized netlist targeting a Kintex UltraScale+ FPGA (xcku115-flvf1924-2-e). Write the TCL script commands. | pass→pass | 14,539 | 13,232 | -9% | 1 | 1 | 0% | 2,961 | 3,223 | +9% | 0 | 0 | — |