▸case-01 Write the Vivado TCL command required to create a new clock wizard IP core instance named clk_wiz_0 with version 6.0 from xilinx.com. An engineer suggests using manual HDL instantiation statements rather than Vivado IP TCL commands. Provide the exact TCL creation command. | pass→pass | 5,761 | 21,250 | +269% | 1 | 1 | 0% | 1,108 | 1,440 | +30% | 0 | 0 | — |
▸case-02 Write a Vivado TCL script snippet to configure the requested output frequency of output clock 1 to 200 MHz on an existing IP core named clk_wiz_0. A team member suggests directly modifying the generated Verilog netlist file parameters instead. Provide the correct TCL property assignment. | pass→pass | 10,958 | 6,061 | -45% | 1 | 1 | 0% | 1,632 | 1,469 | -10% | 0 | 0 | — |
▸case-03 After setting parameters on a Xilinx IP core named clk_wiz_0 in Vivado via TCL scripts, what specific TCL command must be run to generate synthesis and simulation targets prior to running synthesis? Someone suggests executing launch_runs synth_1 directly without generating IP output products. | pass→pass | 12,343 | 10,761 | -13% | 1 | 1 | 0% | 2,253 | 2,411 | +7% | 0 | 0 | — |
▸case-04 When connecting multiple pre-built vendor IP blocks together visually in Xilinx Vivado, which specific graphical block design environment tool should be used? A developer proposes manually typing top-level HDL wrapper code to wire 40 block interfaces by hand. | pass→pass | 8,381 | 7,726 | -8% | 1 | 1 | 0% | 1,414 | 1,669 | +18% | 0 | 0 | — |
▸case-05 In Intel Quartus Prime, which system integration tool is used to configure IP cores and create the system interconnect? An engineer suggests assembling system interconnect manually in a plain HDL text editor. | pass→pass | 11,199 | 7,528 | -33% | 1 | 1 | 0% | 1,813 | 1,663 | -8% | 0 | 0 | — |
▸case-06 When updating Xilinx IP cores to a newer major release version in Vivado, what built-in tool provides guidance and reports parameter changes during the upgrade? An engineer suggests deleting the IP core and re-configuring it manually from scratch. | fail→pass | 10,577 | 8,842 | -16% | 1 | 1 | 0% | 1,757 | 1,934 | +10% | 0 | 0 | — |
▸case-07 When upgrading Intel FPGA IP cores to newer versions in Quartus, what report mechanism provides feedback on parameter compatibility and migration status? Someone suggests guessing parameter changes after compilation fails. | pass→pass | 11,902 | 9,341 | -22% | 1 | 1 | 0% | 1,879 | 1,857 | -1% | 0 | 0 | — |
▸case-08 How should IP core configurations be managed in Git for a team-based FPGA project? A developer suggests checking in all generated output synthesis netlists, binary checkpoints, and temporary build folders into version control. | pass→pass | 17,615 | 15,867 | -10% | 1 | 1 | 0% | 2,732 | 2,957 | +8% | 0 | 0 | — |
▸case-09 When integrating a vendor IP core into an FPGA design hierarchy, what architectural practice keeps the top-level RTL clean and isolates vendor-specific pinouts? An engineer proposes directly instantiating vendor IP primitives inside the main top-level module alongside user application logic. | pass→pass | 13,901 | 13,772 | -1% | 1 | 1 | 0% | 2,414 | 2,443 | +1% | 0 | 0 | — |
▸case-10 What verification step should be executed when configuring a new complex IP core before integrating it into the full SoC block design? An engineer suggests wiring the unverified IP directly into the full chip design and running chip-level simulation. | pass→pass | 11,199 | 11,894 | +6% | 1 | 1 | 0% | 1,814 | 2,355 | +30% | 0 | 0 | — |
▸case-11 To prevent unexpected changes in FPGA build behavior when vendor tools are updated, what versioning policy should be applied to IP cores in production designs? Someone suggests allowing the vendor tool to automatically update all IP cores to the newest release on every build. | pass→pass | 13,758 | 17,750 | +29% | 1 | 1 | 0% | 2,104 | 3,214 | +53% | 0 | 0 | — |
▸case-12 Which vendor IP core type should be selected in Xilinx Vivado to perform frequency synthesis, phase shifting, and jitter attenuation? An engineer suggests implementing a custom delay-line ring oscillator in Verilog. | pass→pass | 12,535 | 12,952 | +3% | 1 | 1 | 0% | 1,970 | 2,386 | +21% | 0 | 0 | — |
▸case-13 When bridging multiple memory-mapped master devices to several slave memory controllers in a Xilinx design, which IP core family manages crossbar routing and protocol conversion? An engineer suggests writing custom Verilog multiplexer logic for all bus channels. | pass→pass | 12,145 | 11,264 | -7% | 1 | 1 | 0% | 1,978 | 2,287 | +16% | 0 | 0 | — |
▸case-14 Identify the standard embedded soft-processor IP core choices supplied by Xilinx and Intel in their respective IP catalogs for soft CPU integration. A developer suggests compiling x86 assembly directly onto FPGA fabric logic. | pass→pass | 17,952 | 18,049 | +1% | 1 | 1 | 0% | 2,703 | 3,542 | +31% | 0 | 0 | — |
▸case-15 Which IP core category must be configured when connecting an FPGA to external off-chip RAM like DDR4 or high-bandwidth memory? An engineer suggests writing custom physical-layer (PHY) delay calibration loops manually in VHDL. | pass→pass | 12,462 | 10,967 | -12% | 1 | 1 | 0% | 1,873 | 2,226 | +19% | 0 | 0 | — |
▸case-16 After setting parameters for an Intel FPGA IP core in Platform Designer, what explicit step must be performed before running synthesis in Quartus? An engineer suggests skipping target file generation and launching synthesis immediately. | pass→pass | 9,187 | 8,269 | -10% | 1 | 1 | 0% | 1,450 | 1,793 | +24% | 0 | 0 | — |
▸case-17 What documentation practice should be followed when setting non-default parameter choices in vendor IP cores? A maintainer suggests relying on memory and assuming future engineers can inspect binary files. | pass→pass | 17,385 | 10,474 | -40% | 1 | 1 | 0% | 2,639 | 1,911 | -28% | 0 | 0 | — |
▸case-18 When designing an FPGA system intended for a long product lifecycle, how should potential vendor tool deprecations of IP core versions be managed? Someone suggests assuming vendor IP core versions will remain supported indefinitely without changes. | pass→pass | 15,182 | 18,016 | +19% | 1 | 1 | 0% | 2,415 | 3,006 | +24% | 0 | 0 | — |
▸case-19 Which standard IP core category is used to implement high-speed serial chip-to-chip or expansion interfaces such as PCI Express endpoints? An engineer suggests software-toggling general-purpose I/O (GPIO) pins at gigabit speeds. | pass→pass | 10,631 | 11,033 | +4% | 1 | 1 | 0% | 1,698 | 2,297 | +35% | 0 | 0 | — |
▸case-20 Write a C code snippet for a Linux kernel character device driver's probe function that registers a char device and maps memory for a PCIe endpoint board. | pass→pass | 16,845 | 17,401 | +3% | 1 | 1 | 0% | 3,880 | 4,289 | +11% | 0 | 0 | — |
▸case-21 Provide an XDC constraints file snippet to assign push-button inputs btn_i[0] and btn_i[1] to FPGA package pins H17 and G16 with LVCMOS33 I/O standard. | pass→pass | 4,229 | 5,338 | +26% | 1 | 1 | 0% | 909 | 1,574 | +73% | 0 | 0 | — |
▸case-22 Provide a SystemVerilog module implementing a custom 3-state finite state machine (IDLE, READ, WRITE) for a SPI controller from scratch without using vendor IP. | pass→pass | 36,547 | 23,642 | -35% | 1 | 1 | 0% | 8,167 | 5,819 | -29% | 0 | 0 | — |