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Deep expertise in VHDL language constructs, IEEE 1076 standard compliance, and synthesis coding guidelines. Expert skill for generating synthesizable VHDL code.
Passed 18 of 22 test cases with the skill, and 15 of 22 without it.
and 2 more in the full report
3 fixed15 passed either way4 still failing0 broke
Tokens, turns and time describe resource use, not a dollar price.
One of 3 test cases the skill fixed. Same model, same prompt, with and without the skill.
Write a parameterized VHDL entity declaration for a configurable shift register with generics for data width (`DATA_WIDTH`, default 16) and depth (`DEPTH`, default 4), using standard logic vector types for input `d` and output `q`.
| Checked | Without skill | With skill |
|---|---|---|
| The generic parameter DEPTH is declared with positive type. | Missed | Passed |
| The port array range uses generic calculation expressions. | Passed | Passed |
The instructions your model reads when the skill loads.
Expert skill for VHDL (VHSIC Hardware Description Language) development following IEEE 1076 standards. Provides deep expertise in synthesizable VHDL code generation, coding guidelines, and best practices for FPGA design.
The VHDL Language skill enables comprehensive VHDL development for FPGA and ASIC designs, supporting:
Generate proper entity and architecture structures:
-- Example: Parameterized FIFO Entity
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity sync_fifo is
generic (
DATA_WIDTH : positive := 8;
DEPTH : positive := 16;
ALMOST_FULL_THRESHOLD : natural := 14;
ALMOST_EMPTY_THRESHOLD : natural := 2
);
port (
clk : in std_logic;
rst_n : in std_logic;
-- Write interface
wr_en : in std_logic;
wr_data : in std_logic_vector(DATA_WIDTH-1 downto 0);
test cases passed, vs 15 / 22 without
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