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Expert-level Verilog and SystemVerilog knowledge following IEEE 1800 standards. Generates synthesizable RTL code with proper coding styles and constructs.
Passed 23 of 24 test cases with the skill, and 20 of 24 without it.
and 4 more in the full report
4 fixed19 passed either way0 still failing1 broke
Tokens, turns and time describe resource use, not a dollar price.
One of 4 test cases the skill fixed. Same model, same prompt, with and without the skill.
I need an AXI-Stream register slice (skid buffer) implementation in modern SystemVerilog conforming to IEEE 1800. Please supply the custom interface definition featuring master, slave, and monitor modports alongside the register buffer module. Along with the HDL code, output a JSON metadata object describing the module structure, parameters, ports, interface connections, RTL compliance verification (such as synthesizability and latch avoidance), and generated file artifact paths.
| Checked | Without skill | With skill |
|---|---|---|
| Output JSON contains top-level keys module, compliance, and artifacts. | Missed | Passed |
| Output JSON compliance object includes boolean field alwaysBlocksCorrect. | Missed | Passed |
| SystemVerilog interface includes master, slave, and monitor modport declarations. | Missed | Passed |
The instructions your model reads when the skill loads.
Expert skill for Verilog and SystemVerilog development following IEEE 1364 and IEEE 1800 standards. Provides deep expertise in synthesizable RTL code generation, proper construct usage, and modern coding practices.
The Verilog/SystemVerilog Language skill enables comprehensive HDL development for FPGA and ASIC designs, supporting:
Use SystemVerilog always block variants correctly:
// Sequential logic - always_ff
always_ff @(posedge clk or negedge rst_n) begin
if (!rst_n) begin
counter <= '0;
state <= IDLE;
end else begin
counter <= counter + 1'b1;
state <= next_state;
end
end
// Combinational logic - always_comb
always_comb begin
// Default assignments prevent latches
next_state = state;
output_valid = 1'b0;
case (state)
test cases passed, vs 20 / 24 without
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