▸case-01 In an IEEE 1800 SystemVerilog property checking an SPI bus request/acknowledge handshaking sequence on `clk`, we need to ignore property evaluation while active-low reset `rst_n` is low (0). A common developer pattern is adding `!rst_n` as an antecedent condition inside the property body. Write the SystemVerilog `property` block for this requirement. | fail→pass | 12,323 | 15,632 | +27% | 1 | 1 | 0% | 1,931 | 2,466 | +28% | 0 | 0 | — |
▸case-02 For an AXI4-Lite bus interface, when `s_axi_arvalid` is high on a clock edge, `s_axi_arready` must also be evaluated on that exact same clock edge to see if the transaction is accepted immediately. Write a SystemVerilog assertion labeled `chk_arvalid_arready` verifying that when `s_axi_arvalid` is asserted, the check for `s_axi_arready` happens on the same cycle. | pass→pass | 23,851 | 12,215 | -49% | 1 | 1 | 0% | 4,913 | 2,795 | -43% | 0 | 0 | — |
▸case-03 In a pipelined memory controller, asserting `req` on clock cycle N must result in `gnt` being high on clock cycle N+1. Write a SystemVerilog property and assertion labeled `chk_req_gnt_next` for this temporal relation. | pass→pass | 8,340 | 5,153 | -38% | 1 | 1 | 0% | 1,182 | 1,276 | +8% | 0 | 0 | — |
▸case-04 In an APB bridge design, we need to assert that whenever the enable signal `penable` transitions from 0 to 1, the select signal `psel` was already high on that clock cycle. Instead of tracking the previous clock cycle value of `penable` in a manual register, write the SystemVerilog assertion `chk_penable_rose`. | pass→pass | 8,323 | 9,956 | +20% | 1 | 1 | 0% | 1,621 | 1,858 | +15% | 0 | 0 | — |
▸case-05 In a handshake protocol, when `frame_valid` transitions from high to low, `frame_error` must be low. Write an SVA assertion `chk_frame_valid_fell` to verify this condition. | pass→pass | 7,728 | 6,209 | -20% | 1 | 1 | 0% | 1,170 | 1,475 | +26% | 0 | 0 | — |
▸case-06 In a memory bus, write an SVA assertion named `chk_addr_stable` ensuring that while `bus_lock` is high, the address bus signal `addr` does not change value from cycle to cycle. | pass→pass | 9,581 | 10,624 | +11% | 1 | 1 | 0% | 1,907 | 1,896 | -1% | 0 | 0 | — |
▸case-07 Inside a procedural `always_comb` block for a 4-to-1 multiplexer with select line `sel`, we want to check immediately that `sel` is never in an invalid state (>= 4). Write the SystemVerilog code snippet to perform this check inside the procedural block. | pass→pass | 9,982 | 6,595 | -34% | 1 | 1 | 0% | 1,538 | 1,525 | -1% | 0 | 0 | — |
▸case-08 When setting up formal verification for an AHB-Lite peripheral module, the formal tool requires constraining the input signal `hready_in` so that the solver never drives illegal stimulus into the module under test. Provide the SystemVerilog assertion code for this formal constraint. | pass→pass | 25,756 | 21,512 | -16% | 1 | 1 | 0% | 4,646 | 4,484 | -3% | 0 | 0 | — |
▸case-09 We want to track functional coverage during simulation to verify that a full 3-phase DMA request sequence (`dma_req` followed 2 cycles later by `dma_ack`, then 1 cycle later by `dma_done`) was exercised at least once. Write the SystemVerilog construct to measure functional coverage of this sequence. | pass→pass | 12,068 | 10,751 | -11% | 1 | 1 | 0% | 1,875 | 1,953 | +4% | 0 | 0 | — |
▸case-10 We have a golden RTL module `fifo_core.sv` that cannot be modified due to strict vendor code freeze. We need to instantiate a set of SVA assertions defined in module `fifo_sva_checks` into all instances of `fifo_core`. Write the SystemVerilog file construct to attach these checks. | pass→pass | 10,758 | 11,500 | +7% | 1 | 1 | 0% | 1,681 | 2,053 | +22% | 0 | 0 | — |
▸case-11 Write an SVA assertion that checks that `valid` implies `data != 0`. Ensure the assertion is named explicitly so that formal tools and simulation logs attribute failures to `check_valid_data_nonzero`. | pass→pass | 8,034 | 7,513 | -6% | 1 | 1 | 0% | 1,167 | 1,675 | +44% | 0 | 0 | — |
▸case-12 A verification engineer wrote a sequence checking that `ready` stays low for 500 consecutive clock cycles using `ready == 0 [*500]`. This sequence causes heavy memory overhead in simulation. How should this long sequence requirement be restructured for better SVA performance? | pass→pass | 21,548 | 15,847 | -26% | 1 | 1 | 0% | 3,199 | 3,094 | -3% | 0 | 0 | — |
▸case-13 A developer is storing 16 intermediate data payloads inside local variables of a complex SVA sequence using `(data_in, v_data = data_in) ##[1:100] (data_out == v_data)`. The simulator is experiencing severe performance degradation. What is the recommended optimization regarding local variables in SVA performance guidelines? | pass→pass | 12,777 | 12,250 | -4% | 1 | 1 | 0% | 2,171 | 2,420 | +11% | 0 | 0 | — |
▸case-14 In a large SystemVerilog SOC project, assertions are currently scattered across individual RTL files. What is the recommended structure for grouping related assertions to maintain clean code separation and facilitate assertion synthesis or formal bind integration? | pass→pass | 19,878 | 18,923 | -5% | 1 | 1 | 0% | 3,126 | 3,198 | +2% | 0 | 0 | — |
▸case-15 When preparing SystemVerilog assertions for hardware emulation or assertion synthesis on FPGA emulators, what design guideline should be followed regarding assertion constructs? | pass→pass | 16,230 | 13,559 | -16% | 1 | 1 | 0% | 2,363 | 2,585 | +9% | 0 | 0 | — |
▸case-16 In a dual-clock asynchronous FIFO, write an SVA concurrent property `prop_cdc_handshake` that checks a signal `src_req` on `src_clk` and evaluates the response `dst_ack` on `dst_clk`. | pass→pass | 18,306 | 22,259 | +22% | 1 | 1 | 0% | 3,272 | 3,841 | +17% | 0 | 0 | — |
▸case-17 Write an immediate assertion inside a SystemVerilog task that checks `bus_width > 0`. If the check fails, it must emit a custom error message using SystemVerilog severity reporting tasks. | pass→pass | 5,076 | 6,048 | +19% | 1 | 1 | 0% | 946 | 1,253 | +32% | 0 | 0 | — |
▸case-18 Write an SVA sequence named `seq_burst` that checks that `bus_enable` remains high for exactly 4 consecutive clock cycles. | fail→pass | 12,981 | 13,882 | +7% | 1 | 1 | 0% | 2,426 | 2,441 | +1% | 0 | 0 | — |
▸case-19 Write an SVA property `prop_event_count` where signal `pkt_valid` must be high 3 times (not necessarily on consecutive clock cycles) before `pkt_done` arrives. | pass→pass | 23,376 | 34,601 | +48% | 1 | 1 | 0% | 4,142 | 5,580 | +35% | 0 | 0 | — |
▸case-20 Write a synthesizable SystemVerilog module `sync_fifo_ctrl` with inputs `clk`, `rst_n`, `push`, `pop`, and outputs `full`, `empty`, `count`. Provide the standard sequential and combinatorial logic for updating `count` and status flags. | pass→pass | 20,010 | 17,683 | -12% | 1 | 1 | 0% | 3,579 | 3,843 | +7% | 0 | 0 | — |
▸case-21 Write a SystemVerilog UVM sequence item class `eth_packet` extending `uvm_sequence_item` with rand fields `src_addr`, `dst_addr`, and `payload`. Include standard UVM field automation macros or constructor. | pass→pass | 8,619 | 7,050 | -18% | 1 | 1 | 0% | 1,402 | 1,754 | +25% | 0 | 0 | — |
▸case-22 Write the SystemVerilog declaration for importing a C language function `compute_crc32` that takes an input byte array and length, returning a 32-bit unsigned int. Provide the SystemVerilog `import` statement. | pass→pass | 6,629 | 6,583 | -1% | 1 | 1 | 0% | 1,178 | 1,428 | +21% | 0 | 0 | — |