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Use when positioning an ASPLOS submission against three communities' literatures at once — covering the architecture, OS/systems, and PL/compiler lanes plus accelerator and prior-ASPLOS lines, handling own-work and arXiv material under the 2027 double-blind rules, and meeting the full-name/DOI citation format.
Passed 21 of 22 test cases with the skill, and 9 of 22 without it.
and 18 more in the full report
12 fixed9 passed either way1 still failing0 broke
Tokens, turns and time describe resource use, not a dollar price.
One of 12 test cases the skill fixed. Same model, same prompt, with and without the skill.
We are running close to the venue reference guidelines. To keep BibTeX entries clean and standard, can we abbreviate co-authors' first names to initials like 'J. Doe' across our bibliography?
| Checked | Without skill | With skill |
|---|---|---|
| Advises writing full first and last names for all co-authors. | Missed | Passed |
| Explains that references are exempt from the submission main body page limit. | Missed | Passed |
The instructions your model reads when the skill loads.
An ASPLOS reviewer pool is assembled from three communities, and each reviewer checks whether their literature is handled competently. Related work at this venue is therefore a coverage problem across parallel lanes — a paper positioned beautifully against the OS literature and blankly against the architecture literature reads as half-researched to half its reviewers.
| Lane | What must be shown | Failure the lane's reviewers spot |
|---|---|---|
| Architecture (ISCA/MICRO/HPCA lineage) | The hardware structure or mechanism is new relative to prior microarchitectural work | Reinvented prefetcher/hint/metadata scheme under a new name |
| OS/systems (SOSP/OSDI/EuroSys/ATC lineage) | The policy/runtime layer differs from existing kernel or hypervisor mechanisms | "The kernel already does this with tunables" |
| PL/compilers (PLDI/POPL/CGO lineage) | Language/compiler-level alternatives are acknowledged when the problem admits them | Hardware solution to a problem the compiler community solved statically |
| Accelerator/domain (when applicable) | Placement in the accelerator design space with honest technology normalization | Comparing against a three-generation-old design point |
| Prior ASPLOS | The intersection lineage itself — what earlier cross-layer attempts did | Missing the exact ASPLOS paper a PC member wrote or shepherded |
For the last lane, mine the venue's own memory: the ACM DL ASPLOS series and the
Influential Paper Award list (see ../../resources/exemplars/library.md) identify
the papers the community regards as canonical for a given boundary.
The distinctive ASPLOS positioning move: prior work usually shares components with yours (a similar hardware structure, a similar kernel policy) while drawing the hardware/software boundary elsewhere. Say precisely where each prior system draws it and why yours moves it:
Template, per closest-prior system:
"<System> provides <capability> at <layer>, which requires <cost/assumption>.
Because it keeps <decision> in <layer>, it cannot <the thing your boundary
placement enables>. We move <decision> to <layer>, which is what makes
<headline property> possible."
Three such paragraphs beat fifteen one-line dismissals — and the systems that get this treatment should be the ones a hostile reviewer would name.
test cases passed, vs 9 / 22 without
More skills from the same source and nearby in the registry, with their headline benchmark lift.