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Get Started Free →brycewang-stanford/asplos-topic-selection
Use when deciding whether a project belongs at ASPLOS or at a single-community venue — applying the cross-layer deletion test, matching against ASPLOS's architecture/PL/OS intersection identity, routing to ISCA/MICRO/HPCA, PLDI/POPL, SOSP/OSDI/EuroSys, SC, or MLSys instead, and choosing between the April and September deadlines.
Passed 20 of 22 test cases with the skill, and 7 of 22 without it.
and 15 more in the full report
13 fixed7 passed either way2 still failing0 broke
Tokens, turns and time describe resource use, not a dollar price.
One of 13 test cases the skill fixed. Same model, same prompt, with and without the skill.
We propose a hardware capability architecture for RISC-V that requires custom Linux kernel page table modifications and memory allocator ABI changes to enforce spatial memory safety. Evaluate venue fit.
| Checked | Without skill | With skill |
|---|---|---|
| Classifies the fit verdict as first-choice ASPLOS | Passed | Passed |
| Lists the modified boundary as the RISC-V capability ISA and kernel allocator ABI | Missed | Passed |
The instructions your model reads when the skill loads.
ASPLOS's self-description is unusually operational: it seeks work that improves the core disciplines — operating systems, programming languages, computer architecture — and their intersection, and its 2027 rapid-review round explicitly prioritizes submissions at that intersection (CFP, checked 2026-07-08). Venue fit is therefore not a prestige question here; it is a screening variable. A technically strong paper that lives cleanly inside one community can be filtered in the first round not because it is bad but because a single-community venue owns its reviewers.
Ask, for each layer the paper touches: if this layer's content were deleted, would a publishable paper remain?
The exemplars library shows what passing looks like in award-validated form: an
accelerator argued from data movement, a scheduler premised on hardware
heterogeneity, an interrupt-delivery boundary redrawn between hypervisor and silicon
(see ../../resources/exemplars/library.md).
| If the core claim is... | Stronger first target | ASPLOS becomes right when... |
|---|---|---|
| A microarchitectural structure (predictor, cache policy, pipeline) | ISCA / MICRO / HPCA | The structure exists to serve a named software behavior, and software changes with it |
| A language design, type system, or compiler optimization | PLDI / POPL / CGO / OOPSLA | The compiler co-evolves with an ISA, accelerator, or OS interface |
| An OS/distributed-systems design on commodity hardware | SOSP / OSDI / EuroSys / ATC | Hardware assumptions are load-bearing: new memory technology, custom hints, near-data compute |
| HPC-scale performance engineering | SC / PPoPP | The result generalizes into an architectural or systems principle beyond one machine |
| ML training/serving systems on stock stacks | MLSys | The ML workload drives a hardware/software interface change, not just better scheduling |
| Security via hardware mechanisms | IEEE S&P / USENIX Security / CCS | The defense requires co-designed architecture + systems support and its evaluation is performance-shaped |
Scope confirmation: the 2027 topics list spans heterogeneous architectures and accelerators; cloud and datacenters; memory, storage, networking, and I/O; power,
test cases passed, vs 7 / 22 without
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